In order to protect an integrated circuit (IC) from external electrostatic voltage and current that might damage its internal devices, ESD protection devices are placed at the input and/or output terminals of the integrated circuit. An ESD device is characterized by having source and drain regions that are provided with large current flow capacity to discharge high electrostatic voltage buildup. The ESD device also has deep or wide junctions between its source/drain and substrate for dissipating heat caused by the large amount of electrostatic current flow.
Since a conventional lightly-doped drain (LDD) MOS transistor is designed to suppress the hot electron effect, its channel current capacity is too small to satisfy the requirements of an ESD device. Further, the areas of drain-substrate and source-substrate junctions of an LDD MOS transistor are not large enough to dissipate the heat from the electrostatic discharge. Therefore a double-diffused drain (DDD) MOS transistor, which has larger channel current capacity and broader areas of source-substrate an drain-substrate junctions than those of LDD MOS transistors, is appealing as an ESD device.
In the past, integrated circuits with ESD protection devices employing LDD MOS transistors have utilized an additional mask step and an additional ion implanting step to increase the doping concentration of the source and drain regions of the LDD MOS transistors that are designed to be ESD devices. The additional ion implantation can be performed before or during the formation of the LDD MOS transistors. However, these further processing steps make the manufacturing process for the integrated circuit very complicated.
FIG. 1A through FIG. 1C are cross-sectional views illustrating the process for forming a DDD MOS ESD device on a silicon substrate 10 during the formation of the LDD MOS transistor. The left hand portions of the drawings depict the regions of LDD MOS transistors, while the right hand portions depict the DDD MOS regions for ESD devices. Referring to FIG. 1A, according to a conventional LDD MOS transistor process, lightly doped regions 12 are formed by ion implanting silicon substrate 10 after sequentially forming a dielectric layer 14 and gate electrodes 15 and 16.
Referring next to FIG. 1B, another dielectric layer is deposited over the structure of FIG. 1A and immediately etched back to leave spacers 18 around gate electrode 15. However, gate electrode 16 in the ESD device region can not be surrounded by spacers for the purpose of forming an ESD device. Therefore a further step of mask protection of the LDD MOS region followed by an etching back step to remove the spacers and dielectric layer 14 in the ESD device region are performed.
The structure of FIG. 1B is then subjected to ion implantation step to form heavily doped regions 19 in silicon substrate 10, as shown in FIG. 1C. The MOS transistor formed in the left hand portion of FIG. 1C has a LDD structure due to the shielding effect of spacers 18. At the same time, due to the absence of spacers around gate electrode 16, the transistor in the right hand portion of FIG. 1C has source and drain regions with double diffused structures, and is provided with ESD properties.
Another example, as shown in cross-sectional views from FIG. 2A to FIG. 2C, forms the DDD MOS ESD structure prior to the formation of the LDD structure. There are also two portions in the drawings to show the LDD MOS region and ESD device region respectively.
Referring to FIG. 2A, an ion implantation step is performed to form lightly doped regions 22 in a silicon substrate 20 after the formation of a dielectric layer 24 and gate electrodes 25 and 26. Instead of forming spacers around gate electrode 25, an additional photoresist mask 28 is formed over the LDD MOS region, which serves as an ion implantation barrier layer, as is shown in FIG. 2B. The process is continued by performing an ion implantation step to form heavily doped source and drain regions 29 in silicon substrate 20, as illustrated in the right hand portion of FIG. 2C. The DDD structure is thus formed in the ESD device region after this ion implantation step. After removing photoresist mask 28, the process goes on according to the conventional LDD manufacturing steps and thus its description and drawings are omitted here.
Note that at least one additional mask and one extra ion implantation step are necessary in the above mentioned process flows for forming the DDD MOS ESD device. As a matter of fact, in a well-established integrated circuit processing sequence, the addition of any supplementary steps will severely affect the consistency of the products, thus increasing the manufacturing cost.